INFO:EDK:2526 - This project was created with version older than EDK 14.7!! INFO:EDK:2817 - XPS will update the project to EDK 14.7 INFO:EDK:2841 - Your current files will be saved with . extension Reving up design to EDK 14.7... WARNING: log file xps_proj.log not found Xilinx EDK 12.0 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Format revision from 11.5 to 12.0 completed. Design files have changed while updating the design from 11.5 to 12.0 Creating a back up of 11.5 design files... Creating backup of xps_proj.mhs as xps_proj_mhs.11.5 Creating backup of xps_proj.mss as xps_proj_mss.11.5 Moving all revup related files to 'revup' folder... Xilinx EDK 12.1 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.12.0 Format revision from 12.0 to 12.1 completed. No changes to design files while updating the design from 12.0 to 12.1 Moving all revup related files to 'revup' folder... Xilinx EDK 12.2 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.12.1 Format revision from 12.1 to 12.2 completed. No changes to design files while updating the design from 12.1 to 12.2 Moving all revup related files to 'revup' folder... Xilinx EDK 12.3 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.12.2 Format revision from 12.2 to 12.3 completed. No changes to design files while updating the design from 12.2 to 12.3 Moving all revup related files to 'revup' folder... Xilinx EDK 12.4 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.12.3 Format revision from 12.3 to 12.4 completed. No changes to design files while updating the design from 12.3 to 12.4 Moving all revup related files to 'revup' folder... Xilinx EDK 13.1 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.12.4 Writing xps_proj.xmp ... EDK version 13.1 UPDATE: Removing Software Project information from xps_proj.xmp Removing XmdStub and BootLoop information from xps_proj.xmp Elf file information is preserved based on InitBram value.. Elf files are not existing in D:/MyDoc/1-Xilinx/ISE/14.7/886-TDM_14.7/sz130-v147_1 location....Hence ElfSim and ElfImp fields in xps_proj.xmp will be empty.. Format revision from 12.4 to 13.1 completed. Design files have changed while updating the design from 12.4 to 13.1 Creating a back up of 12.4 design files... Creating backup of xps_proj.mhs as xps_proj_mhs.12.4 Moving all revup related files to 'revup' folder... Xilinx EDK 13.2 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.13.1 Format revision from 13.1 to 13.2 completed. No changes to design files while updating the design from 13.1 to 13.2 Moving all revup related files to 'revup' folder... Xilinx EDK 13.3 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.13.2 Format revision from 13.2 to 13.3 completed. No changes to design files while updating the design from 13.2 to 13.3 Moving all revup related files to 'revup' folder... Xilinx EDK 13.4 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.13.3 Format revision from 13.3 to 13.4 completed. No changes to design files while updating the design from 13.3 to 13.4 Moving all revup related files to 'revup' folder... Xilinx EDK 14.1 Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.13.4 Format revision from 13.4 to 14.1 completed. No changes to design files while updating the design from 13.4 to 14.1 Moving all revup related files to 'revup' folder... Xilinx EDK 14.2 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.14.1 Format revision from 14.1 to 14.2 completed. No changes to design files while updating the design from 14.1 to 14.2 Moving all revup related files to 'revup' folder... Xilinx EDK 14.3 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.14.2 Format revision from 14.2 to 14.3 completed. No changes to design files while updating the design from 14.2 to 14.3 Moving all revup related files to 'revup' folder... Xilinx EDK 14.4 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.14.3 Format revision from 14.3 to 14.4 completed. No changes to design files while updating the design from 14.3 to 14.4 Moving all revup related files to 'revup' folder... Xilinx EDK 14.5 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.14.4 Format revision from 14.4 to 14.5 completed. No changes to design files while updating the design from 14.4 to 14.5 Moving all revup related files to 'revup' folder... Xilinx EDK 14.6 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.14.5 Format revision from 14.5 to 14.6 completed. No changes to design files while updating the design from 14.5 to 14.6 Moving all revup related files to 'revup' folder... Xilinx EDK 14.7 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Input File: xps_proj.xmp Creating backup of xps_proj.log as xps_proj_log.14.6 Format revision from 14.6 to 14.7 completed. No changes to design files while updating the design from 14.6 to 14.7 Moving all revup related files to 'revup' folder... Format revision of project to EDK 14.7 completed INFO:EDK - Project Files updated successfully. Now trying to update IP versions... ERROR:EDK:4110 - IPNAME: microblaze, INSTANCE: microblaze_i - cannot find MPD for the pcore 'microblaze_v7_20_d' in any of the repositories - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 39 ERROR:EDK:4110 - IPNAME: microblaze, INSTANCE: microblaze_i - cannot find MPD for the pcore 'microblaze_v7_20_d' in any of the repositories - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 39 WARNING:EDK:4088 - IPNAME: xps_uartlite, INSTANCE: uart_console - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 174 WARNING:EDK:4088 - IPNAME: xps_timer, INSTANCE: timer_system - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 189 WARNING:EDK:4088 - IPNAME: plb_v46, INSTANCE: mb_plb - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 199 WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: i_lmb - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 207 WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: d_lmb - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 214 WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: d_lmb_bram_cntlr - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 228 WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: i_lmb_bram_cntlr - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 237 WARNING:EDK:4088 - IPNAME: xps_intc, INSTANCE: intc_system - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 246 WARNING:EDK:4088 - IPNAME: xps_spi, INSTANCE: spi_cntlr - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 270 ERROR:EDK:4110 - IPNAME: dcm_module, INSTANCE: dcm_multi - cannot find MPD for the pcore 'dcm_module_v1_00_d' in any of the repositories - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 284 ERROR:EDK:4110 - IPNAME: dcm_module, INSTANCE: dcm - cannot find MPD for the pcore 'dcm_module_v1_00_d' in any of the repositories - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 297 WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: reset_system - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 338 ERROR:EDK:4111 - IPNAME: microblaze, INSTANCE: microblaze_i - cannot find MPD for the pcore - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 39 ERROR:EDK:4111 - IPNAME: dcm_module, INSTANCE: dcm_multi - cannot find MPD for the pcore - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 284 ERROR:EDK:4111 - IPNAME: dcm_module, INSTANCE: dcm - cannot find MPD for the pcore - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 297 Done. WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_i - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 39 WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: i_lmb - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 207 WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: d_lmb - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 214 WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: d_lmb_bram_cntlr - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 228 WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: i_lmb_bram_cntlr - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 237 WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: reset_system - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 338 WARNING:EDK:4088 - IPNAME: microblaze, INSTANCE: microblaze_i - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 39 WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: i_lmb - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 207 WARNING:EDK:4088 - IPNAME: lmb_v10, INSTANCE: d_lmb - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 214 WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: d_lmb_bram_cntlr - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 228 WARNING:EDK:4088 - IPNAME: lmb_bram_if_cntlr, INSTANCE: i_lmb_bram_cntlr - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 237 WARNING:EDK:4088 - IPNAME: proc_sys_reset, INSTANCE: reset_system - Superseded core for architecture 'spartan3e' - D:\MyDoc\1-Xilinx\ISE\14.7\886-TDM_14.7\sz130-v147_1\xps_proj.mhs line 338